A semiconductor wafer is typically composed of a substrate, such as a silicon wafer, on which a plurality of transistors have been formed. Transistors are chemically and physically connected into the substrate and are interconnected through the use of well known multilevel coplanar interconnects to form functional circuits. Typical multilevel interconnects are comprised of stacked thin-films consisting of, for example, one or more of the following: titanium (Ti), titanium nitrate (TiN), copper (Cu), aluminum (Al), tungsten (W), tantalum (Ta), or any combination thereof.
The traditional technique for forming functional multilevel coplanar interconnects has involved planarizing the surface of the interconnects via chemical-mechanical polishing (CMP). CMP involves the concurrent chemical and mechanical polishing of an overlying first layer to expose the surface of a non-planar second layer on which the first layer has been formed.
CMP compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries) typically contain an abrasive material in a liquid carrier and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. Polishing compositions are typically used in conjunction with polishing pads (e.g., a polishing cloth or disk). Instead of, or in addition to, being suspended in the polishing composition, the abrasive material may be incorporated into the polishing pad.
Because of the desire for faster devices in the microelectronics industry, there is an interest in using elements from Groups III-V of the Periodic Table because of their high electron mobility. The rapid electron transport offered by the Group III-V materials allows for greater electrical conductivity in smaller features (i.e., allowing for advanced-node integrated circuits) as compared with copper which suffers from much lower electron mobility and is limited in application to larger features.
A significant challenge with using Group III-V materials in the microelectronics industry is achieving a smooth and planar surface to enable further processing. Effective planarization with good removal rates of Group III-V materials is difficult to achieve because of smaller feature size and material selectivity requirements for front-end advanced nodes. Another challenge with using Group III-V materials in semiconductor wafers is that during planarization, the Group III-V materials are susceptible to producing toxic outgases, which can be irritating, flammable, and even poisonous. For example, a toxic gaseous hydride species can be produced such as arsine (AsH3) or phosphine (PH3). These gases are a significant hazard. Conventional approaches have required the need to handle the post CMP slurry contaminated waste through ventilation systems, which are cumbersome and costly.
Thus, there remains a need in the art for polishing compositions and methods that can provide desirable polishing performance including effective removal rates of the Group III-V materials. It is also desired to provide effective polishing performance of Group III-V materials while controlling the output of toxic outgases.